(1) Field of the Invention
The invention relates to the fabrication of Integrated Circuit (IC) devices and, more particularly, to a method for forming a high value poly resistor of accurate value that is required in mixed-mode configurations, that is applications where capacitors coexist with logic applications on the same Integrated Circuit.
(2) Description of the Prior Art
The developments in the semiconductor industry have, similar to developments in many other industries, been driven by improved semiconductor device performance at reduced cost. The semiconductor industry serves and addresses the data processing industry (computers and the like) and a significant number of peripheral applications (video games and the like) in the entertainment industry. What these applications have in common is that data is handled in digital form and that the functions that are performed by the semiconductor devices are functions of data manipulation or functions of data storage. The former category of functions is also referred to as logic functions, the latter category as memory functions. Since these functions are of a different nature, they have typically been provided by semiconductor devices that address either the logic function or the storage functions but not both simultaneously. This does not imply that no semiconductor device was ever created that did not incorporate both functions. In fact, efforts are being made where, due to a potential increase in device functionality and performance gained at no or at a minimal increment in cost, both the logic functions and the storage functions are provided by the same semiconductor device. Increased use of the chip can also in some instances be achieved by a functional sharing or integration of device features or device functions between the two indicated digital disciplines of logic and storage. Further addressed by this approach is the always important reduction of device and functional interconnect whereby, by mounting devices of logic and storage closely together, device performance can be improved by reducing interconnect resistivity, capacitive coupling, contact resistance, propagation delay and other important electrical performance inhibitors. In present day DRAM devices, capacitive charge and de-charge characteristics are key to high-speed device performance. These characteristics can be improved by, among others, reducing the distance between the storage element (the capacitive storage node) and surrounding elements of logic or device switching.
Where the trend in the semiconductor industry is toward increased use of digital processing, that is processing based on on-off or zero-one conditions in the device circuitry, there are still applications where analog signals, that is signals that have a time dependent value that can vary within a range of values without being restricted to being either one or zero, are being used. Capacitors form a basic component of many of these analog circuits that are used for analog applications such as switched capacitor filters. It is well known in the art that capacitors are widely applied in digital applications such as the storage node for Dynamic Random Access Memory (DRAM) circuits. This ability of capacitors to function in either the digital or the analog mode is referred to as the mixed mode application of the capacitor.
The making of electrical contacts with the various points of interest in a semiconductor device, for instance source and drain regions together with the gate electrode of a Field Effect Transistor (FET), is typically accomplished with the formation of a layer of silicide over the surface of the point of contact for easy and low resistance connectivity. The thereby encountered problem of mask alignment (that is required for the required sequential exposures) is solved by making the process of forming the layer of silicide self-aligned with for instance the gate electrode. From this has emerged the designation of salicide processes which refers to the creation of self-aligned (layers of) silicide. The layer of silicide is formed by the deposition of a layer of reactive metal, such as titanium or cobalt, over the surface of silicon (substrate) where the layer of silicide needs to be formed. The reactive metal is annealed with the underlying silicon forming silicides such as TiSi.sub.2 over the regions where low resistance electrical contact must be established.
One of the components that is required for certain semiconductor devices, such as for instance Static Random Access Memory (SRAM) devices, is a resistive load. A resistive load component can, in its simplest form, be created by sandwiching a lightly doped layer of polysilicon between two points of electrical contact. To the points of electrical contact can be connected for instance metal of polysilicon interconnect lines or interconnect lines that are created by N+ diffusion (thereby forming low resistance interconnect lines). The sandwiched layer of poly serves as a resistor, which typically has a high resistive value. Increased N+ dopant concentration in the poly will decrease the resistive value of the poly, another parameter that can be used to manipulate the resistive value is by the selection of the cross section of the layer of poly in a plane that is essentially perpendicular to the flow of current through the layer of poly. An increased surface area of the cross section will decrease the value of the resistance and visa versa. Where the resistor load is applied to the SRAM, the resistor must make electrical contact with the gate electrode and the drain region of the pull-down transistor as well as to the metal line to pass gate transistor. A resistor tab that makes contact with the gate and the drain regions can be created by depositing dopants at the interfaces between these regions and the resistive load. Electrical contact must however be established with the drain region whereby an opening is created to the drain region in the surface of the substrate, this creation of the opening to the drain region removes a significant amount of the dopant from the surface of the substrate in the drain region. This dopant has as yet not been driven into the surface of the substrate by a high temperature-processing step. In sum: the light doping of the poly determines the resistive value of the resistive load, the resistive load is interconnected to the surrounding components by means of a high dope implant on either side of the resistor for which a doping mask is used.
For mixed signal, that is combined digital and analog signal applications, it is required that the resistive load has a high value of ohmic resistance. The value of this ohmic resistance must further be within tight limits; the ohmic resistance must also remain within these tight limits when creating the resistive load within a manufacturing environment and over an extended period of time. Currently, POCl.sub.3 is used as a dopant for the polysilicon of the resistive load; this dopant however exhibits a significant amount of lateral diffusion making exact control of the resistive value of the load resistance very difficult to achieve. The blanket implant methodology that is used to establish the interconnect points for the resistive load also does not lend itself to tight implant control due to the fact that a lower thermal budget with high implant energy is used for this implant. The implant mask used during this process further does not accurately define the resistive load. A method must therefore be provided that allows better control of the resistive value of the load resistor while at the same time allowing for tight control of the design parameters that determine the interconnect of the resistive load.
U.S. Pat. No. 5,866,451 (Yoo et al.) shows a process for a mixed mode capacitor with a SRAM and poly resistor. However, this reference differs from the invention.
U.S. Pat. No. 5,543,350 (Chi et al.) shows a SRAM resistor process
U.S. Pat. No. 5,652,174 (Wuu et al.) teaches a SRAM poly resistor method.
U.S. Pat. No. 5,843,815 (Liaw) recites a method for a SRAM having poly load resistors.